The present invention relates generally to integrated circuits and, more particularly, to a process for forming dual damascene structures and capacitors in an integrated circuit.
Interdigitized or finger capacitors are being used more in integrated circuits as the height of metal lines in the integrated circuits become greater than the space between the metal lines. This occurs because device dimensions are decreasing which results in a corresponding decrease in distance between metal lines. Interdigitized or finger capacitors employ sidewall capacitance, the capacitance produced between adjacent metal lines to form a capacitor.
One example of a finger capacitor is shown in U.S. Pat. No. 6,037,621 entitled ON CHIP CAPACITOR STRUCTURE and issued to Wilson. This patent is incorporated herein by reference. The concept of using sidewall capacitance to form capacitors is also discussed in a recent paper entitled Fractal Capacitors, H. Samavati, et al., 1998 ISSCC, Session 16, TD: Advanced Radio-Frequency Circuits, Paper FP 16.6, 256-57, which is incorporated herein by reference. The paper points out that sidewall or fringing capacitance yields a higher capacitance per unit area than conventional parallel plate capacitors as the distance between the plates decreases.
In addition to device dimension decreases, there has been trend to use dual damascene structures instead of single damascene structures. Single damascene is an interconnection fabrication process for integrated circuits in which grooves are formed in an insulating layer and filled with a conductive material to form interconnects. Dual damascene is a multi-level interconnection process in which, in addition to forming the grooves of single damascene, conductive contact (or via) openings are also formed in the insulating layer. A conductive material is formed in the grooves and conductive contact (or via) openings. The inventor has recognized the need to combine these trends to provide a sidewall capacitor in an integrated circuit also including a dual damascene structure.
The present invention is directed to a process for forming a dual damascene structure and a capacitor. The process includes forming a stack including insulating layers and a stop layer. The stack is patterned so that the openings used to form the sidewall capacitors may be formed when the vias or grooves of the dual damascene structure are formed. In this way, the process for manufacturing the sidewall capacitors may be integrated with the dual damascene process without adding additional mask or etching steps.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.